From a22bfb36c4c89595bda6aa6da1bf4f1ff738380a Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 27 Sep 2017 17:48:48 +0100 Subject: [PATCH 1/2] coresight: ETM: Add support for ARM Cortex-A73 Add ARM Cortex A-73 ETM PIDs to the known ETM ips. While at it also add description of the CPU to which the ETM belongs, to make it easier to identify the ETM devices. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm4x.c | 22 ++++++++++++------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index cf364a514c121b..376485731e72a0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1034,7 +1034,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) } pm_runtime_put(&adev->dev); - dev_info(dev, "%s initialized\n", (char *)id->data); + dev_info(dev, "CPU%d: %s initialized\n", + drvdata->cpu, (char *)id->data); if (boot_enable) { coresight_enable(drvdata->csdev); @@ -1052,21 +1053,26 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return ret; } -static const struct amba_id etm4_ids[] = { - { /* ETM 4.0 - Cortex-A53 */ +static struct amba_id etm4_ids[] = { + { .id = 0x000bb95d, .mask = 0x000fffff, - .data = "ETM 4.0", + .data = "Cortex-A53 ETM v4.0", }, - { /* ETM 4.0 - Cortex-A57 */ + { .id = 0x000bb95e, .mask = 0x000fffff, - .data = "ETM 4.0", + .data = "Cortex-A57 ETM v4.0", }, - { /* ETM 4.0 - A72, Maia, HiSilicon */ + { .id = 0x000bb95a, .mask = 0x000fffff, - .data = "ETM 4.0", + .data = "Cortex-A72 ETM v4.0", + }, + { + .id = 0x000bb959, + .mask = 0x000fffff, + .data = "Cortex-A73 ETM v4.0", }, { 0, 0}, }; From c4f8eaffd3d4a7b246495c95a3f52786ad9d2635 Mon Sep 17 00:00:00 2001 From: Robert Walker Date: Mon, 16 Oct 2017 10:27:55 +0100 Subject: [PATCH 2/2] coresight: Fix disabling of CoreSight TPIU The CoreSight TPIU should be disabled when tracing to other sinks to allow them to operate at full bandwidth. This patch fixes tpiu_disable_hw() to correctly disable the TPIU by configuring the TPIU to stop on flush, initiating a manual flush, waiting for the flush to complete and then waits for the TPIU to indicate it has stopped. Signed-off-by: Robert Walker --- drivers/hwtracing/coresight/coresight-tpiu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index d7a3e453016d8d..735dca089389ac 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -46,8 +46,11 @@ #define TPIU_ITATBCTR0 0xef8 /** register definition **/ +/* FFSR - 0x300 */ +#define FFSR_FT_STOPPED BIT(1) /* FFCR - 0x304 */ #define FFCR_FON_MAN BIT(6) +#define FFCR_STOP_FI BIT(12) /** * @base: memory mapped base address for this component. @@ -85,10 +88,14 @@ static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) { CS_UNLOCK(drvdata->base); - /* Clear formatter controle reg. */ - writel_relaxed(0x0, drvdata->base + TPIU_FFCR); + /* Clear formatter and stop on flush */ + writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR); /* Generate manual flush */ - writel_relaxed(FFCR_FON_MAN, drvdata->base + TPIU_FFCR); + writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR); + /* Wait for flush to complete */ + coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN, 0); + /* Wait for formatter to stop */ + coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED, 1); CS_LOCK(drvdata->base); }