From 634599056d477267defe3e85d35e19f90678fe45 Mon Sep 17 00:00:00 2001 From: talhaiqbal-10xe Date: Mon, 26 Aug 2024 14:55:10 +0500 Subject: [PATCH] Update README.md --- README.md | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 4ca7a4f..ccde134 100644 --- a/README.md +++ b/README.md @@ -1,19 +1,22 @@ # Infinite-ISP Infinite-ISP is a full-stack ISP development platform designed for all aspects of a hardware ISP. It includes a collection of camera pipeline modules written in Python, a fixed-point reference model, an optimized RTL design, an FPGA integration framework and its associated firmware ready for Xilinx® Kria KV260 development board. The platform features a stand-alone Python-based Tuning Tool that allows tuning of ISP parameters for different sensors and applications. Finally, it also offers a software solution for Linux by providing required drivers and a custom application development stack to bring Infinite-ISP to the Linux platforms. -![](docs/assets/Infinite-ISP_Repo_Flow.png) + +![](assets/Infinite-ISP_Repo_Flow.png) | Sr. | Repository name | Description | |---------| ------------- | ------------- | | 1 | **[Infinite-ISP_AlgorithmDesign](https://github.com/10x-Engineers/Infinite-ISP)** | Python based model of the Infinite-ISP pipeline for algorithm development | -| 2 | **[Infinite-ISP_ReferenceModel](https://github.com/10x-Engineers/Infinite-ISP_ReferenceModel)** :anchor:| Python based fixed-point model of the Infinite-ISP pipeline for hardware implementation | -| 3 | **[Infinite-ISP_RTL](https://github.com/10x-Engineers/Infinite-ISP_RTL)** | RTL Verilog design of the image signal processor based on the Reference Model **[(Request Access)](https://docs.google.com/forms/d/e/1FAIpQLSfOIldU_Gx5h1yQEHjGbazcUu0tUbZBe0h9IrGcGljC5b4I-g/viewform?usp=sharing)**| -| 4 | **[Infinite-ISP_Automated_Testing](https://github.com/10x-Engineers/Infinite-ISP_Automated_Testing)** | A framework to enable the automated block and multi-block level testing of the image signal processor to ensure a bit accurate design | -| 5 | **FPGA Implementation** | FPGA implementation of Infinite-ISP on
| +| 2 | **[Infinite-ISP_ReferenceModel](https://github.com/10x-Engineers/Infinite-ISP_ReferenceModel)** :anchor: | Python based fixed-point model of the Infinite-ISP pipeline for hardware implementation | +| 3 | **[Infinite-ISP_RTL](https://github.com/10x-Engineers/Infinite-ISP_RTL)** | RTL Verilog design of the image signal processor based on the Reference Model | +| 4 | **[Infinite-ISP_AutomatedTesting](https://github.com/10x-Engineers/Infinite-ISP_AutomatedTesting)** | A framework to enable the automated block and multi-block level testing of the image signal processor to ensure a bit accurate design | +| 5 | **FPGA Implementation** | FPGA implementation of Infinite-ISP on
| | 6 | **[Infinite-ISP_FPGABinaries](https://github.com/10x-Engineers/Infinite-ISP_FPGABinaries)** | FPGA binaries (bitstream + firmware executable) for the Xilinx® Kria KV260’s XCK26 Zynq UltraScale + MPSoC| | 7 | **[Infinite-ISP_TuningTool](https://github.com/10x-Engineers/Infinite-ISP_TuningTool)** | Collection of calibration and analysis tools for the Infinite-ISP | | 8 | **[Infinite-ISP_LinuxCameraStack](https://github.com/10x-Engineers/Infinite-ISP_LinuxCameraStack.git)** | Extending Linux support to Infinite-ISP and the developement of Linux-based camera application stack | +**[Request Access](https://docs.google.com/forms/d/e/1FAIpQLSfOIldU_Gx5h1yQEHjGbazcUu0tUbZBe0h9IrGcGljC5b4I-g/viewform?usp=sharing)** to **Infinite_ISP-RTL, Infinite-ISP_AutomatedTesting** and **Infinite-ISP_FPGA_XCK26** repositories + # Infinite-ISP Reference Model: A Python-based Model for RTL Implementation of Camera Pipeline Modules